Mapping switch-level simulation onto gate-level hardware accelerators - Design Automation Conference, 1991. 28th ACM/IEEE
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چکیده
In this paper, we present a framework for performing switchlevel simulation on hardware accelerators. A symbolic analyzer preprocesses the MOS network into a functionally equivalent Boolean representation. The analyzer thus converts switch-level simulation into a task of evaluating Boolean expressions. Our approach maps the Boolean r e p resentation into the instruction set of the hardware accelerator. The resultant framework supports switch level simulation on a class of hardware accelerators that traditionally have been limited to gate-level simulation.
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تاریخ انتشار 2004